An interrupt is a signal that is generated by a component of a computing device or a peripheral device to ‘interrupt’ the processing of a processing unit. The processing unit is then able to deal with an interrupt event relating to the component or peripheral device before returning to the interrupted processing. Interrupt signals are generally asynchronous, and as such difficult to predict and manage. In a typical system, when a processing unit receives an interrupt signal, the present processing is interrupted and in its place program code is loaded from memory and processed by the processing unit to handle the associated interrupt event. This program code typically comprises an interrupt handling routine provided by an operating system. For example, a computing device comprising a modem may connect to a network. In this case, an interrupt signal may be generated by a modem device when a network connection is made or lost (an interrupt event); an interrupt handling routine may thus update control variables to indicate a current status of the connection and, if necessary, reconnect.
In more advanced application-specific integrated circuits (ASICs) and so-called system-on-chip (SoC) configurations, there may be multiple components, multiple peripheral devices and multiple processing units. Many of these systems are designed to provide real-time responses. Each interrupt source may generate a variety of interrupt signals, and different processing units may require different interrupt handling functions. For example, an interrupt event for a particular system module may require a dedicated interrupt handling routine, which in turn may require a dedicated service on each processing unit.
Moreover, a computing device may comprise a number of interconnected subsystems, with each subsystem having a dedicated processing unit and one or more computing components. A peripheral device may have couplings to more than one subsystem. In this case, different interrupt systems relating to each subsystem may be required as it is difficult to share interrupt signals between different processing units. The complexity of such systems may also be difficult to manage if each subsystem is performing different operations in parallel. For example, it may be difficult to accurate map the dependencies between the subsystems during use, making it difficult to design and implement interrupt handling systems.
U.S. Pat. No. 7,328,294 B2 describes an interrupt system for handling interrupt events in a multiprocessor system. This publication describes the typical problems encountered in a real time system with multiple interrupt sources. It describes a solution involving an interrupt controller that can receive input from a variety of interrupt sources, such as peripheral components and peripheral interfaces. Characteristics of an interrupt signal are then used by the interrupt controller to select a processing unit to run a routine for handling the associated interrupt event.
U.S. Pat. No. 7,610,425 B2, also published as U.S. Pat. No. 7,581,052 B1 and US 2007/0043347 A1, describes an interrupt daemon that monitors the interrupt signal load among a number of processing units that results from an initial mapping of the interrupts to the processing units. The interrupt daemon determines whether there is a sufficient imbalance of the interrupt signals among the processing units and, if so, triggers a reassignment routine that generates a new mapping of the interrupt signals among the processing units. A similar technique is described in U.S. Pat. No. 6,237,058 B1.
While these solutions offer some improvement, the complexity of managing interrupts in electronic or computing systems with multiple components and/or processing units remains. For example, the interrupt signal load at a system-wide level is maintained even though interrupt distribution among processing units is modified. Existing solutions also require a number of software and/or hardware redesigns making them difficult to implement.
There is thus a need in the art for an improved interrupt management system that can manage high interrupt loads, is flexible, and is easy to implement in a large variety of systems. In particular, there is a need for interrupt management systems that are particularly suited to the requirements of complex embedded and mobile systems.